4-bit Full Adder using two-input NAND Gates
Addition is one of the most commonly used arithmetic
operations. And its operation leads to the application in digital circuits,
like the adder/summer. The full adder/summer performs the addition of numbers.
And its component is very essential especially in the arithmetic logic unit(s),
digital signal processing, and in micro-processors. This circuit is my project for my course and I want it to share with you. I am tasked to design a 4-bit full adder (FA) using only two-input NAND gates.
In this paper, a schematic diagram and an IC layout of a 4-bit full adder were
made and simulated in order to compare the acquired output waveform, both from
the schematic simulation and IC layout aiming to grasp the concept behind
lay-outing limiting/lessening any parasitic effect and having more compact
circuit.
The binary adder circuit is an important building
block of digital arithmetic circuits. Hence it becomes one of the most critical
components of a processor, as it is used in the arithmetic logic unit (ALU), in
the floating-point unit, and for address generation in case of cache or memory
access. The 4-bit full adder’s performance would affect the system as a whole
since more transistors will be used which will add more time delay.
FA is a
combinational circuit that forms the arithmetic sum of 3 bits. It consists of 3
inputs and 2 outputs. The design of a binary adder begins by considering the
process of addition in base 2. For example,
1 1
1
0 1 1
= 11
+
0 1 1 0 =
6
1 0 0
0 1 =
17
Implementing a full adder must satisfy the expected
output based in its truth table.
Full-adder Truth Table
From the truth table we will only get the expression
for the equation, for the sum and the carry, of a 1-bit full adder. In order to
implement a logical sequence of a 4-bit full adder, four pieces of 1-bit full
adder arranged in series and will do the circuit. And using the NAND
counterpart of the OR, NAND, and XOR gates.
In
addition to its main task, which is adding binary numbers, it is the nucleus of
many other useful operations such as subtraction, Multiplication, division,
addresses calculation, etc. In most of these systems the adder is part of the critical path that
determines the overall performance of the system. That is why enhancing the
performance of the 1-bit full-adder cell (the building block of the binary
adder) is a significant goal.
- System Block Diagram
The 1-bit full adder can be implemented using NAND gates only,
1-bit full adder configuration
In order to form an adder capable of adding multi-bit numbers, the 1-bit full adder, in Figure 1, will be replicated and by connecting the carry-out of the 1-bit full adder to the carry-in of the full adder for the next significant bit.
4-bit ripple adder circuit
- NMOS-PMOS Transistor Schematic Diagram
The CMOS (complementary metal-oxide-semiconductor) technology is used predominantly to create digital circuitry. The CMOS gates circuits are constructed in such a way that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor.
The basic idea for CMOS technology is to combine P-type and N-type MOSFETs such that there is never a conducting path from the supply voltage to ground. As a consequence, CMOS circuits consume very little energy.
Truth Table of NAND Gate
Two Input NAND Gate
The PDN network consists of two NMOS devices in series that conduct when both A and Bare high. The PUN is the dual net-work, and consists of two parallel PMOS transistors. This means that F is 1 if A = 0 or B =0, which is equivalent to F = A·B. The truth table for the simple two input NAND gate is given in Table 2. It can be verified that the output F is always connected to either VDD or GND, but never to both at the same time.
The CMOS (complementary metal-oxide-semiconductor) technology is used predominantly to create digital circuitry. The CMOS gates circuits are constructed in such a way that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor.
The basic idea for CMOS technology is to combine P-type and N-type MOSFETs such that there is never a conducting path from the supply voltage to ground. As a consequence, CMOS circuits consume very little energy.
Combining these ideas, we will come up with a 4-bit full adder, using only NAND gates. The final circuit is shown below:
4-bit Full Adder Using NAND Gate
The waveform of the input and output of the full adder were shown below:
Input waveform for the 4-bit Full Adder
Output waveforms of the 4-bit Full Adder
Sources of power consumption such as glitches and short-circuit currents can be minimized by careful circuit design and transistor sizing. More transistors mean more parasitic components were added to the circuit which contributed to the distortion of the output waveforms.
View Full Adder tutorial Fully https://youtu.be/nJs1lIfBmoo Click here , Full & Half Adder Tutorial
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